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data sheet description the pd17p709a is produced by replacing the on-chip mask rom of the pd17704a, 17705a, 17707a, 17708a, and 17709a with a one-time prom. the pd17p709a allows programs to be written once, so the pd17p709a is suitable for preproduction in pd17704a, 17705a, 17707a, 17708a, or 17709a system development or low-volume production. when reading this document, also refer to the publications on the pd17704a, 17705a, 17707a, 17708a, or 17709a. the electrical characteristics (including power supply current) and pll analog characteristics of the pd17p709a differ from those of the pd17704a, 17705a, 17707a, 17708a, and 17709a. in high-volume application set production, be sure to carefully check these differences. features compatible with the pd17704a, 17705a, 17707a, 17708a, and 17709a on-chip one-time prom: 32 kb (16384 16 bits) supply voltage: v dd = 5 v 10% ordering information part number package pd17p709agc-3b9 80-pin plastic qfp (14 14) mos integrated circuit 4-bit single-chip microcontroller with dedicated hardware for digital tuning system pd17p709a document no. u15723ej1v0ds00 (1st edition) date published october 2001 n cp(k) printed in japan 2001 ? the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
pd17p709a 2 data sheet u15723ej1v0ds functional outline (1/2) part number pd17704a pd17705a pd17707a pd17708a pd17709a pd17p709a item program memory (rom) 8192 16 bits 12288 16 bits 16384 16 bits 16384 16 bits (mask rom) (mask rom) (mask rom) (one-time prom) general-purpose data memory (ram) 672 4 bits 1120 4 bits 1176 4 bits instruction execution time 1.78 s (with f x = 4.5 mhz crystal oscillator) general-purpose ports i/o ports: 46 input ports: 12 output ports: 4 stack levels address stack: 15 levels interrupt stack: 4 levels dbf stack: 4 levels (can be manipulated via software) interrupts external: 6 sources (falling edge of ce pin, int0 to int4) internal: 6 sources (timers 0 to 3, serial interfaces 0 and 1) timer 5 channels basic timer (clock: 10, 20, 50, 100 hz): 1 channel 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 khz): 1 channel 8-bit timer (clock: 1 khz, 2 khz, 10 khz, 100 khz): 2 channels 8-bit timer multiplexed with pwm (clock: 440 hz, 4.4 khz): 1 channel a/d converter 8 bits 6 channels (hardware mode and software mode selectable) d/a converter (pwm) 3 channels (8-bit or 9-bit resolution selectable by software) output frequency: 4.4 khz, 440 hz (with 8-bit pwm selected) 2.2 khz, 220 hz (with 9-bit pwm selected) serial interface 2 units (3 channels) 3-wire serial i/o: 2 channels 2-wire serial i/o/i 2 c bus: 1 channel pll division mode direct division mode (vcol pin (mf mode): 0.5 to 3 mhz) pulse swallow mode (vcol pin (hf mode): 10 to 40 mhz) (vcoh pin (vhf mode): 60 to 130 mhz) reference frequency 13 types selectable (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50 khz) charge pump two error-out output pins (eo0, eo1) phase comparator unlock status detectable by program intermediate frequency counter intermediate frequency (if) measurement p1c0/fmifc pin: 10 to 11 mhz in fmif mode 0.4 to 0.5 mhz in amif mode p1c1/amifc pin: 0.4 to 0.5 mhz in amif mode external gate width measurement p2a1/fcg1, p2a0/fcg0 pin beep output 2 pins output frequency: 1 khz, 3 khz, 4 khz, 6.7 khz (beep0 pin) 67 hz, 200 hz, 3 khz, 4 khz (beep1 pin)
3 pd17p709a data sheet u15723ej1v0ds part number pd17704a pd17705a pd17707a pd17708a pd17709a pd17p709a item reset power-on reset (on power application) reset by reset pin watchdog timer reset can be set only once on power application: 65536 instructions, 131072 instructions, or no-use selectable stack pointer overflow/underflow reset can be set only once on power application: interrupt stack or address stack selectable ce reset (ce pin low high level) ce reset delay timing can be set. power failure detection function standby clock stop mode (stop) halt mode (halt) supply voltage pll operation: v dd = 4.5 to 5.5 v cpu operation: v dd = 3.5 to 5.5 v package 80-pin plastic qfp (14 14) (2/2)
pd17p709a 4 data sheet u15723ej1v0ds pin configuration (top view) 80-pin plastic qfp (14 14) pd17p709agc-3b9 (1) normal operation mode 22 gnd2 p0d3/ad3 p0d2/ad2 p0d1/ad1 p0d0/ad0 p1c3/ad5 p1c2/ad4 p1c1/amifc p1c0/fmifc v dd 1 vcoh vcol gnd1 eo0 eo1 test p1d3 p1d2 p1d1/beep1 p1d0/beep0 int2 p1a3/int4 p1a2/int3 p1a1 p1a0/tm0g p3a3 p3a2 p3a1 p3a0 p3b3 p3b2 p3b1 p3b0 p2a2 p2a1/fcg1 p2a0/fcg0 p1b3 p1b2/pwm2 p1b1/pwm1 p1b0/pwm0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p0c2 p0c3 p2c0 p2c1 p2c2 p2c3 p3d0 p3d1 p3d2 p3d3 p3c0 p3c1 p3c2 p3c3 p2b0 p2b1 p2b2 p2b3 int0 int1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 reset v dd 0 ce x in x out gnd0 reg p2d0 p2d1 p2d2 p0b0/si1 p0b1/so1 p0b2/sck1 p0b3/si0 p0a0/so0 p0a1/sck0 p0a2/scl p0a3/sda p0c0 p0c1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
5 pd17p709a data sheet u15723ej1v0ds (2) prom programming mode note connect to the same potential as v dd . caution the items in parentheses indicate the processing of pins not used in the prom programming mode. l: independently connect to gnd via a resistor (470 ? ) h: independently connect each pin to v dd via a resistor (470 ? ) open: leave open. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (h) v dd 0 (l) clk (open) gnd0 reg gnd2 md3 md2 md1 md0 v dd 1 gnd1 v pp d0 d1 d2 d3 d4 d5 d6 d7 (l) (l) note (l) (open) (l) (l) (l) (open) (l)
pd17p709a 6 data sheet u15723ej1v0ds pin names ad0 to ad5: a/d converter input amifc: am frequency counter input beep0, beep1: beep output ce: chip enable clk: address update clock input d0 to d7: data i/o eo0, eo1: error-out output fcg0, fgc1: frequency counter gate input fmifc: fm frequency counter input gnd0 to gnd2: ground 0 to 2 int0 to int4: external interrupt input md0 to md3: operation mode selection pwm0 to pwm2: d/a converter output p0a0 to p0a3: port 0a p0b0 to p0b3: port 0b p0c0 to p0c3: port 0c p0d0 to p0d3: port 0d p1a0 to p1a3: port 1a p1b0 to p1b3: port 1b p1c0 to p1c3: port 1c p1d0 to p1d3: port 1d p2a0 to p2a2: port 2a p2b0 to p2b3: port 2b p2c0 to p2c3: port 2c p2d0 to p2d2: port 2d p3a0 to p3a3: port 3a p3b0 to p3b3: port 3b p3c0 to p3c3: port 3c p3d0 to p3d3: port 3d reg: cpu regulator reset: reset input sck0, sck1: 3-wire serial clock i/o scl: 2-wire serial clock i/o sda: 2-wire serial data i/o si0, si1: 3-wire serial data input so0, so1: 3-wire serial data output test: test input tm0g: timer 0 gate input vcoh: local oscillation high input vcol: local oscillation low input v dd 0, v dd 1: power supply v pp : program voltage application x in , x out : main clock oscillation
7 pd17p709a data sheet u15723ej1v0ds block diagram 4 4 ad0/p0d0 ad5/p1c3 ad1/p0d1 ad2/p0d2 ad3/p0d3 ad4/p1c2 4 4 4 4 4 4 4 3 4 4 3 4 4 4 p0a0 to p0a3 p0b0 to p0b3 p0c0 to p0c3 p0d0 to p0d3 p1a0 to p1a3 p1b0 to p1b3 p1c0 (md0) to p1c3 (md3) p1d0 to p1d3 p2a0 to p2a2 p2b0 to p2b3 p2c0 (d0) to p2c3 (d3) p2d0 to p2d2 p3a0 to p3a3 p3b0 to p3b3 p3c0 to p3c3 p3d0 (d4) to p3d3 (d7) pwm2/p1b2 pwm0/p1b0 pwm1/p1b1 ports a/d converter d/a converter 8-bit timer 3 basic timer rf ram 1776 4 bits sysreg alu instruction decoder one-time prom 16384 16 bits program counter stack vcoh vcol eo0 eo1 pll so0/p0a0 sck0/p0a1 scl/p0a2 sda/p0a3 si0/p0b3 sck1/p0b2 so1/p0b1 si1/p0b0 beep0/p1d0 beep1/p1d1 int0 int1 int2 int3/p1a2 int4/p1a3 fcg0/p2a0 fcg1/p2a1 fmifc/p1c0 amifc/p1c1 tm0g/p1a0 x in x out ce reset v dd 0, v dd 1 reg v cpu cpu peripheral gnd0 to gnd2 serial interface 0 serial interface 1 beep interrupt control frequency counter 8-bit timer 0 gate counter 8-bit timer 1 8-bit timer 2 osc reset regulator remark pins in parentheses are used in prom programming mode.
pd17p709a 8 data sheet u15723ej1v0ds contents 1. pin functions ................................................................................................................ .............. 9 1.1 pin function list ........................................................................................................... ....... 9 1.2 prom programming mode ................................................................................................. 13 1.3 equivalent circuits of pins ................................................................................................. 14 1.4 connections of unused pins .............................................................................................. 19 1.5 cautions on using ce, int0 to int4, and reset pins (only in normal operation mode) ...................................................................................... 21 1.6 cautions on using test pin (only in normal operation mode) ..................................... 21 2. one-time prom (program memory) write, read, and verify .................................... 22 2.1 operation modes for program memory write, read and verify ...................................... 23 2.2 program memory write procedure .................................................................................... 24 2.3 program memory read procedure ..................................................................................... 25 3. electrical specifications .................................................................................................. ....... 26 4. package drawing ............................................................................................................ ..............31 5. recommended soldering conditions ................................................................................... 32 appendix development tools .................................................................................................... .. 33
9 pd17p709a data sheet u15723ej1v0ds 1. pin functions 1.1 pin function list pin no. symbol function output form 1 int2 edge-detectable vectored interrupt input pins. rising or falling edge can be 41 int1 specified. 42 int0 2 p1a3/int4 port 1a multiplexed with external interrupt request signal input and event 3 p1a2/int3 signal input pins. 4 p1a1 p1a3 to p1a0 5 p1a0/tm0g 4-bit input port int4, int3 edge-detectable vectored interrupt tm0g input for gate of 8-bit timer 0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained (p1a3 to p1a0) (p1a3 to p1a0) 6 p3a3 4-bit i/o port. cmos | | input or output can be specified in 4-bit units. push-pull 9 p3a0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 10 p3b3 4-bit i/o port. cmos | | input or output can be specified in 4-bit units. push-pull 13 p3b0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 14 p2a2 port 2a multiplexed with external gate counter input pins. cmos 15 p2a1/fcg1 p2a2 to p2a0 push-pull 16 p2a0/fcg0 3-bit i/o port input or output can be specified in 1-bit units. fcg1, fcg0 input for external gate counter after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained (p2a2 to p2a0) (p2a2 to p2a0) (p2a2 to p2a0) (p2a2 to p2a0)
pd17p709a 10 data sheet u15723ej1v0ds pin no. symbol function output form 17 p1b3 port 1b multiplexed with d/a converter output pins. n-ch 18 p1b2/pwm2 p1b3 to p1b0 open-drain | | 4-bit output port (12 v 20 p1b0/pwm0 pwm2 to p2m0 withstanding 8- or 9-bit d/a converter output voltage) after reset with clock stopped power-on reset wdt&sp reset ce reset outputs low level outputs low level retained retained (p1b3 to p1b0) (p1b3 to p1b0) (p1b3 to p1b0) 21 gnd2 ground 33 gnd1 75 gnd0 22 p0d3/ad3 port 0d multiplexed with a/d converter input pins | | p0d3 to p0d0 25 p0d0/ad0 4-bit input port pull-down resistors can be connected in 1-bit units. ad3 to ad0 analog input of a/d converter with 8-bit resolution after reset with clock stopped power-on reset wdt&sp reset ce reset input with pull-down input with pull-down retained retained resistor resistor (p0d3 to p0d0) (p0d3 to p0d0) 26 p1c3/ad5 port 1c multiplexed with a/d converter input and if counter input pins. 27 p1c2/ad4 p1c3 to p1c0 28 p1c1/amifc 4-bit input port 29 p1c0/fmifc ad5, ad4 analog input to a/d converter with 8-bit resolution fmifc, amifc input to frequency counter after reset with clock stopped power-on reset wdt&sp reset ce reset input input p1c3/ad5, p1c3/ad5, (p1c3 to p1c0) (p1c3 to p1c0) p1c2/ad4 p1c2/ad4 retained retained p1c1/amifc, p1c1/amifc, p1c0/fmifc p1c0/fmifc input input (p1c1, p1c0) (p1c1, p1c0)
11 pd17p709a data sheet u15723ej1v0ds pin no. symbol function output form 30 v dd 1 power supply. supply the same voltage to these pins. 79 v dd 0 with cpu and peripheral function operating: 4.5 to 5.5 v with cpu operating: 3.5 to 5.5 v with clock stopped: 2.2 to 5.5 v 31 vcoh pll local oscillation (vco) frequency input. 32 vcol vcoh active with vhf mode selected by program; otherwise, pulled down. vcol active with hf or mw mode selected by program; otherwise, pulled down. because the input of these pins goes into an ac amplifier, cut the dc component of the input signal with a capacitor. 34 eo0 output from charge pump of pll frequency synthesizer. outputs the divided cmos 35 eo1 frequency of local oscillation and the result of comparison of the phase 3-state difference of the reference frequency. after reset with clock stopped power-on reset wdt&sp reset ce reset high-impedance high-impedance high-impendance high-impedance output output output output 36 test test input pin. be sure to connect this pin to gnd. 37 p1d3 port 1d and beep output. cmos 38 p1d2 p1d3 to p1d0 push-pull 39 p1d1/beep1 4-bit i/o port 40 p1d0/beep0 input or output can be specified in 1-bit units. beep1, beep0 beep output after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained (p1d3 to p1d0) (p1d3 to p1d0) (p1d3 to p1d0) (p1d3 to p1d0) 43 p2b3 4-bit i/o port. cmos | | input or output can be specified in 1-bit units. push-pull 46 p2b0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 47 p3c3 4-bit i/o port. cmos | | input or output can be specified in 4-bit units. push-pull 50 p3c0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained
pd17p709a 12 data sheet u15723ej1v0ds pin no. symbol function output form 51 p3d3 4-bit i/o port. cmos | | input or output can be specified in 4-bit units. push-pull 54 p3d0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 55 p2c3 4-bit i/o port. cmos | | input or output can be specified in 4-bit units. push-pull 58 p2c0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 59 p0c3 4-bit i/o port. cmos | | input or output can be specified in 4-bit units. push-pull 62 p0c0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 63 p0a3/dsa ports p0a and p0b are multiplexed with i/o of serial interface. n-ch 64 p0a2/scl p0a3 to p0a0 open-drain 65 p0a1/sck0 4-bit i/o port cmos 66 p0a0/so0 input or output can be specified in 1-bit units. push-pull 67 p0b3/si0 p0b3 to p0b0 68 p0b2/sck1 4-bit i/o port 69 p0b1/so1 input or output can be specified in 1-bit units. 70 p0b0/si1 sda, scl serial data and serial clock i/o of serial interface 0 in 2-wire serial i/o or i 2 c bus mode sck0, so0, si0 serial clock i/o, serial data output, and serial data input of serial interface 0 in 3-wire serial i/o mode sck1, so1, si1 serial clock i/o, serial data output, serial data input of serial interface 1 in 3-wire serial i/o mode after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained p0a3 to p0a0, p0a3 to p0a0, p0a3 to p0a0, p0a3 to p0a0, p0b3 to p0b0 p0b3 to p0b0 p0b3 to p0b0 p0b3 to p0b0 71 p2d2 3-bit i/o port. cmos | | input or output can be specified in 1-bit units. push-pull 73 p2d0 after reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained
13 pd17p709a data sheet u15723ej1v0ds pin no. symbol function output form 74 reg cpu regulator. connect this pin to gnd via 0.1 f capacitor. 76 x out ground pins of crystal resonator. 77 x in 78 ce device operation selection, ce reset, and interrupt signal input pin. device operation selection when ce is high, the pll frequency synthesizer can operate. when ce is low, the pll frequency synthesizer is automatically disabled internally. ce reset when ce goes high, the device is reset at the rising edge of the internal basic timer setting pulse. this pin also has a reset timing delay function. interrupt a vectored interrupt occurs at the falling edge of this pin. 80 reset reset input pin no. symbol function output form 26 md3 input for operating mode selection for program memory write, read, or | | verify. 29 md0 21 gnd2 ground 33 gnd1 75 gnd0 36 v pp pin to which program voltage is applied during program memory write, read, or verify. +12.5 v is applied. 30 v dd 1 power supply pins. +6 v is applied during program memory write, read, or 79 v dd 0 verify. 51 d7 8-bit data i/o for program memory write, read, or verify cmos push-pull | | 58 d0 77 clk clock input for address updating during program memory write, read, or verify 1.2 prom programming mode remark the pins other than those listed above are not used in prom programming mode. for the handling of the unused pins, see pin configuration (2) prom programming mode .
pd17p709a 14 data sheet u15723ej1v0ds 1.3 equivalent circuits of pins (1) p0a (p0a1/sck0, p0a0/so0) p0b (p0b3/si0, p0b2/sck1, p0b1/so1, p0b0/si1) p0c (p0c3, p0c2, p0c1, p0c0) p1d (p1d3, p1d2, p1d1/beep1, p1d0/beep0) p2a (p2a2, p2a1/fcg1, p2a0/fcg0) p2b (p2b3, p2b2, p2b1, p2b0) (i/o) p2c (p2c3, p2c2, p2c1, p2c0) p2d (p2d2, p2d1, p2d0) p3a (p3a3, p3a2, p3a1, p3a0) p3b (p3b3, p3b2, p3b1, p3b0) p3c (p3c3, p3c2, p3c1, p3c0) p3d (p3d3, p3d2, p3d1, p3d0) note this is an internal signal that is output when the clock stop instruction is executed. its circuit is designed not to increase the current consumption due to noise even if it is floated. v dd v dd ckstop note
15 pd17p709a data sheet u15723ej1v0ds (2) p0a (p0a3/sda, p0a2/scl) (i/o) note this is an internal signal that is output when the clock stop instruction is executed. its circuit is designed not to increase the current consumption due to noise even if it is floated. (3) p1b (p1b3, p1b2/pwm2, p1b1/pwm1, p1b0/pwm0) (output) (4) p0d (p0d3/ad3, p0d2/ad2, p0d1/ad1, p0d0/ad0) (input) note this is an internal signal that is output when the clock stop instruction is executed. its circuit is designed not to increase the current consumption due to noise even if it is floated. v dd ckstop note v dd ckstop note a/d converter p0dpld flag high on-resistance
pd17p709a 16 data sheet u15723ej1v0ds (5) p1a (p1a1) (input) (6) p1c (p1c3/ad5, p1c2/ad4) (input) (7) p1c (p1c1/amifc, p1c0/fmifc) (input) v dd v dd a/d converter v dd v dd v dd general-purpose port high on-resistance frequency counter
17 pd17p709a data sheet u15723ej1v0ds (8) ce reset int0, int1, int2 (schmitt-triggered input) p1a (p1a3/int4, p1a2/int3, p1a0/tm0g) (9) x out (output), x in (input) (10) eo1, eo0 (output) v dd v dd dwn up v dd v dd high on-resistance internal clock high on- resistance x in x out
pd17p709a 18 data sheet u15723ej1v0ds (11) vcoh, vcol (input) v dd v dd high on-resistance high on- resistance
19 pd17p709a data sheet u15723ej1v0ds 1.4 connections of unused pins it is recommended to connect unused pins as follows. table 1-1. connections of unused pins (1/2) pin name i/o mode recommended connection port pin p0d3/ad3 to p0d0/ad0 input independently connect to gnd via a resistor note 1 . p1c3/ad5 p1c2/ad4 p1c1/amifc note 2 set to port mode and individually connect to v dd or gnd p1c0/fmifc note 2 via a resistor note 1 . p1a3/int4 independently connect to gnd via a resistor note 1 . p1a2/int3 p1a1 p1a0/tm0g p1b3 n-ch open-drain set to low-level output by software and leave open. p1b2/pwm2 to p1b0/pwm0 output p0a3/sda i/o note 3 set to general-purpose input port mode by software and p0a2/scl independently connect to v dd or gnd via a resistor note 1 . p0a1/sck0 p0a0/so0 p0b3/si0 p0b2/sck1 p0b1/so1 p0b0/si1 p0c3 to p0c0 p1d3 p1d2 p1d1/beep1 p1d0/beep0 p2a2 p2a1/fcg1 p2a0/fcg0 p2b3 to p2b0 p2c3 to p2c0 p2d2 to p2d0 notes 1. if a pin is externally pulled up (connected to v dd via a resistor) or pulled down (connected to gnd via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. generally, the resistance of a pull-up or pull- down resistor is several 10 k ? , although it depends on the application circuit. 2. do not set these pins as amifc and fmifc pins; otherwise, the current consumption will increase. 3. the i/o ports are set in the general-purpose input port mode at power-on reset, when reset by the reset pin, or when reset by an overflow or underflow of the watchdog timer or the stack.
pd17p709a 20 data sheet u15723ej1v0ds table 1-1. connections of unused pins (2/2) pin name i/o mode recommended connection port pin p3a3 to p3a0 i/o note 2 set in general-purpose input port mode by software and p3b3 to p3b0 independently connect to v dd or gnd via a resistor note 1 . p3c3 to p3c0 p3d3 to p3d0 non-port ce input connect to v dd via a resistor note 1 . pins eo1 output leave open. eo0 int0 to int2 input independently connect to gnd via a resistor note 1 . reset input connect to v dd via a resistor note 1 . test directly connect to gnd. vcoh input disable pll via software and leave open. vcol notes 1. if a pin is externally pulled up (connected to v dd via a resistor) or pulled down (connected to gnd via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. generally, the resistance of a pull-up or pull- down resistor is several 10 k ? , although it depends on the application circuit. 2. the i/o ports are set in the general-purpose input port mode at power-on reset, when reset by the reset pin, or when reset by an overflow or underflow of the watchdog timer or the stack.
21 pd17p709a data sheet u15723ej1v0ds 1.5 cautions on using ce, int0 to int4, and reset pins (only in normal operation mode) the ce, int0 to int4, and reset pins have a function to set a test mode in which the internal operations of the pd17p709a are tested (ic test), in addition to the functions listed in 1.1 pin function list . when a voltage exceeding v dd is applied to any of these pins, the device is set in the test mode. if a noise exceeding v dd is superimposed during normal operation, therefore, the test mode is set by mistake, affecting the normal operation. especially if the wiring length of pins is too long, noise is superimposed on these pins. in consequence, the above problem occurs. therefore, keep the wiring length as short as possible to prevent noise from being superimposed. if superimposition of noise is unavoidable, connect an external component as illustrated below to suppress the noise. ? connect a diode with a low v f connect a capacitor between the pin and between the pin and v dd .v dd . 1.6 cautions on using test pin (only in normal operation mode) when v dd is applied to the test pin, the device is set in the test mode or program memory write/verify mode. therefore, be sure to keep the wiring length of this pin as short as possible, and directly connect it to the gnd pin. if the wiring length between the test pin and gnd pin is too long, or if external noise is superimposed on the test pin, generating a potential difference between the test pin and gnd pin, your program may not run normally. gnd test short ce, int0 to int4, reset v dd ce, int0 to int4, reset v dd diode with low v f v dd v dd
pd17p709a 22 data sheet u15723ej1v0ds 2. one-time prom (program memory) write, read, and verify the pd17p709a includes a 16,384 16-bit one-time prom program memory. in normal operation, this prom is accessed in 16-bit word units. during program memory write, read, and verify, the prom is accessed in 8-bit word units. the higher 8 bits of a 16-bit word are located at an even-numbered address, and the lower 8 bits are located at an odd-numbered address. the pins used for the write, read, and verify operations of this one-time prom are listed in table 2-1. clock input from the clk pin, instead of address input, is used for updating addresses. table 2-1. pins used for program memory write, read, and verify pin name function v pp program voltage application (+12.5 v) clk address update clock input md0 to md3 operation mode selection d0 to d7 8-bit data i/o v dd 0, v dd 1 supply voltage application (+6 v) the specified prom programmer and a dedicated programmer adapter are used for writing to the on-chip prom. the following prom programmers and programmer adapters are usable. prom programmer programmer adapter pg-1500 pa17p709gc + pa-17kdz (adapter for pg-1500) third-party prom programmers are also available, such as the af-9703, af-9704, af-9705, and af-9706 (manufactured by ando electric co., ltd.)
23 pd17p709a data sheet u15723ej1v0ds figure 2-1. pa-17p709gc and pa-17kdz 2.1 operation modes for program memory write, read, and verify when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the pd17p709a enters the program memory write, read, and verify mode. the following operation modes can be set by setting pins md0 to md3 as shown below. pins not listed in table 2-2 should be connected to gnd via a pull-down resistor (470 ? ) (refer to pin configuration (2) prom programming mode ). table 2-2. operation mode setting for program memory write, read, and verify operation mode setting operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l program memory address 0-clear mode l h h h write mode l l h h write/verify mode h h h program inhibit mode remark : l or h to pg-1500 pa-17p709gc pa-17kdz
pd17p709a 24 data sheet u15723ej1v0ds 2.2 program memory write procedure program memory can be written at high speed using the following procedure. (1) pull down unused pins to gnd via a resistor. set the clk pin to low. (2) supply 5 v to the v dd pin. set the v pp pin to low. (3) wait for 10 s and then supply 5 v to the v pp pin. (4) set the mode setting pin to program memory address 0-clear mode. (5) supply +6 v to the v dd pin and +12.5 v to the v pp pin. (6) set the program inhibit mode. (7) write data in the 1 ms write mode. (8) set the program inhibit mode. (9) set the verify mode. if the data is correct, go to step (10). if not, repeat steps (7) to (9). (10) (x: number of write operations from steps (7) to (9)) 1 ms additional write. (11) set the program inhibit mode. (12) input four pulses to the clk pin to increment the program memory address by one. (13) repeat steps (7) to (12) until the end address is reached. (14) set the program memory address 0-clear mode. (15) change the v dd and v pp pins to 5 v. (16) turn off the power. the following figure shows steps (2) to (12). reset write verify additional write address increment x repetitions data input data output data input hi - z hi - z hi - z hi - z v dd + 1 v dd gnd v dd v pp v dd gnd v pp clk d0 to d7 md0 md1 md2 md3
25 pd17p709a data sheet u15723ej1v0ds 2.3 program memory read procedure (1) pull down unused pins to gnd via a resistor. set the clk pin to low. (2) supply 5 v to the v dd pin. set the v pp pin to low. (3) wait for 10 s and then supply 5 v to the v pp pin. (4) set the mode setting pin to program memory address 0-clear mode. (5) supply +6 v to the v dd pin and +12.5 v to the v pp pin. (6) set the program inhibit mode. (7) set the verify mode. addresses are incremented by one for each 4-pulse cycle input to the clk pin. (8) set the program inhibit mode. (9) set the program memory address 0-clear mode. (10) change the v dd and v pp pins to 5 v. (11) turn off the power. the following figure shows steps (2) to (9). data output hi - z hi - z v dd + 1 v dd gnd v dd v pp v dd gnd v pp clk d0 to d7 md0 md1 md2 md3 data output ? reset
26 pd17p709a data sheet u15723ej1v0ds 3. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.0 v prom program voltage v pp ?.3 to +13.5 v input voltage v i other than ce, int0 to int4, and reset pins ?.3 to v dd + 0.3 v ce, int0 to int4, and reset pins ?.3 to v dd + 0.6 v output voltage v o except p1b0 to p1b3 ?.3 to v dd + 0.3 v output current, high i oh per pin ?.0 ma total of p2a0 to p2a2, p3a0 to p3a3, ?5.0 ma and p3b0 to p3b3 total of p0a0 to p0a3, p0b0 to p0b3, p0c0 to p0c3, ?5.0 ma p1d0 to p1d3, p2b0 to p2b3, p2c0 to p2c3, p2d0 to p2d2, p3c0 to p3c3, and p3d0 to p3d3 output current, low i ol per pin for p1b0 to p1b3 12.0 ma per pin for p1b0 to p1b3 8.0 ma total of p2a0 to p2a2, p3a0 to p3a3, 15.0 ma and p3b0 to p3b3 total of p0a0 to p0a3, p0b0 to p0b3, p0c0 to p0c3, 25.0 ma p1d0 to p1d3, p2b0 to p2b3, p2c0 to p2c3, p2d0 to p2d2, p3c0 to p3c3, and p3d0 to p3d3 total of p1b0 to p1b3 pins 25.0 ma output voltage v bds p1b0 to p1b3 14.0 v total power dissipation p t 200 mw operating ambient t a ?0 to +85 c temperature storage temperature t stg ?5 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 when cpu and pll are operating 4.5 5.0 5.5 v v dd2 when cpu and pll are stopped 3.5 5.0 5.5 v recommended output withstanding voltage (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit output withstanding v bds p1b0 to p1b3 12 v voltage
27 pd17p709a data sheet u15723ej1v0ds dc characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current i dd1 when cpu is operating and pll is stopped with 1.5 3.0 ma sine wave input to x in pin. (f in = 4.5 mhz 1%, v in = v dd ) i dd2 when cpu and pll are stopped with sine-wave 0.7 1.5 ma input to x in pin. (f in = 4.5 mhz 1%, v in = v dd ) with halt instruction data retention voltage v ddr1 crystal oscillation 3.5 5.5 v v ddr2 crystal oscillation power failure detection by timer ff 2.2 5.5 v v ddr3 stopped data memory retained 2.0 5.5 v data retention current i ddr1 crystal oscillation v dd = 5 v, t a = 25 c 2.0 4.0 a i ddr2 stopped 2.0 30.0 a input voltage, high v ih1 p0a0, p0b1, p0c0 to p0c3, p1a0, p1a1, p1c0 to 0.7v dd v dd v p1c3, p1d0 to p1d3, p2a2, p2b0 to p2b3, p2c0 to p2c3, p2d0 to p2d2, p3a0 to p3a3, p3b0 to p3b3, p3c0 to p3c3, p3d0 to p3d3 v ih2 p0a1 to p0a3, p0b0, p0b2, p0b3, p2a0, p2a1, ce, 0.8v dd v dd v int0 to int4, reset v ih3 p0d0 to p0d3 0.55v dd v dd v input voltage, low v il1 p0a0, p0b1, p0c0 to p0c3, p1a0, p1a1, p1c0 to 0 0.3v dd v p1c3, p1d0 to p1d3, p2a2, p2b0 to p2b3, p2c0 to p2c3, p2d0 to p2d2, p3a0 to p3a3, p3b0 to p3b3, p3c0 to p3c3, p3d0 to p3d3 v il2 p0a1 to p0a3, p0b0, p0b2, p0b3, p2a0, p2a1, ce, 0 0.2v dd v int0 to int4, reset v il3 p0d0 to p0d3 0 0.15v dd v output current, high i oh1 p0a0 to p0a3, p0b0 to p0b3, p0c0 to p0c3, 1.0 ma p1d0 to p1d3, p2a0 to p2a2, p2b0 to p2b3, p2c0 to p2c3, p2d0 to p2d2, p3a0 to p3a3, p3b0 to p3b3, p3c0 to p3c3, p3d0 to p3d3 v oh = v dd 1 v i oh2 eo0, eo1 v dd = 4.5 to 5.5 v, v oh = v dd 1 v 3.0 ma output current, low i ol1 p0a0 to p0a3, p0b0 to p0b3, p0c0 to p0c3, 1.0 ma p1d0 to p1d3, p2a0 to p2a2, p2b0 to p2b3, p2c0 to p2c3, p2d0 to p2d2, p3a0 to pa3a, p3b0 to p3b3, p3c0 to p3c3, p3d0 to p3d3 v ol = 1 v i ol2 eo0, eo1 v dd = 4.5 to 5.5 v, v ol = 1 v 3.0 ma i ol3 p1b0 to p1b3 v ol = 1 v 7.0 ma input current, high i ih p0d0 to p0d3 pulled down v in = v dd 5.0 150 a output off leakage i lo1 p1b0 to p1b3 v in = 12 v 1.0 a current i lo2 eo0, eo1 v in = v dd , v in = 0 v 1.0 a input leakage current, i lih input pin v in = v dd 1.0 a high input leakage current, low i lil input pin v in = 0 v 1.0 a
28 pd17p709a data sheet u15723ej1v0ds ac characteristics (t a = ?0 to +85 c, v dd = 5 v 10%) parameter symbol conditions min. typ. max. unit operating frequency f in1 vcol pin, sine-wave input v in = 0.15v p-p 0.8 3 mhz mf mode sine-wave input v in = 0.1v p-p 0.5 3 mhz f in2 vcol pin, hf mode, sine-wave input 10 40 mhz v in = 0.1v p-p note f in3 vcoh pin, vhf mode, sine-wave input 60 130 mhz v in = 0.1v p-p note f in4 amifc pin, sine-wave input 0.4 0.5 mhz v in = 0.15v p-p f in5 fmifc pin, fmif count mode, sine-wave input 10 11 mhz v in = 0.20v p-p f in6 fmifc pin, amif count mode, sine-wave input 0.4 0.5 mhz v in = 0.15v p-p sio0 input frequency f in7 external clock 1 mhz sio1 input frequency f in8 external clock 0.7 mhz note the condition of sine-wave input v in = 0.1v p-p is the rated value when the pd17p709a is operating alone. where influence of noise must be taken into consideration, operation under input amplitude conditions of v in = 0.15v p-p is recommended. a/d converter characteristics (t a = ?0 to +85 c, v dd = 5 v 10%) parameter symbol conditions min. typ. max. unit a/d conversion total error 8 bits 3.0 lsb a/d conversion total error 8 bits t a = 0 to 85 c 2.5 lsb reference characteristics (t a = +25 c, v dd = 5.0 v) parameter symbol conditions min. typ. max. unit supply current i dd3 when cpu and pll are operating with sine-wave 6.0 12.0 ma input to vcoh pin (f in = 130 mhz, v in = 0.3v p-p ) dc programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 pins other than clk 0.7v dd v dd v v ih2 clk v dd 0.5 v dd v input voltage, low v il1 pins other than clk 0 0.2v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 a output voltage, high v oh i oh = 1 ma v dd 1.0 v output voltage, low v ol i ol = 1 ma 1.0 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. ensure that v pp does not exceed +13.5 v including overshoot. 2. v dd must be applied before v pp , and cut after v pp .
29 pd17p709a data sheet u15723ej1v0ds ac programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) parameter symbol conditions min. typ. max. unit address setup time note (to md0 )t as 2 s md1 setup time (to md0 )t m1s 2 s data setup time (to md0 )t ds 2 s address hold time note (from md0 )t ah 2 s data hold time (from md0 )t dh 2 s delay time from md0 to data output float t df 0 130 ns v pp setup time (to md3 )t vps 2 s v dd setup time (to md3 )t vds 2 s initial program pulse width t pw 0.95 1.0 1.05 ms additional program pulse width t opw 0.95 21.0 ms md0 setup time (to md1 )t m0s 2 s delay time from md0 to data output t dv md0 = md1 = v il 1 s md1 hold time (from md0 )t m1h t m1h + t m1r 50 s2 s md1 recovery time (from md0 )t m1r 2 s program counter reset time t pcr 10 s clk input high-/low-level widths t xh , t xl 0.125 s clk input frequency f x 4.19 mhz initial mode setting time t i 2 s md3 setup time (to md1 )t m3s 2 s md3 hold time (from md1 )t m3h 2 s md3 setup time (to md0 )t m3sr program memory read 2 s delay time from address note to data output t dad program memory read 2 s hold time from address note to data output t had program memory read 0 130 ns md3 hold time (from md0 )t m3hr program memory read 2 s delay time from md3 to data output float t dfr program memory read 2 s reset setup time t res 10 s note the internal address signal is incremented by 1 on the 3rd fall of a four-clock input (clk) cycle, and is not connected to a pin.
30 pd17p709a data sheet u15723ej1v0ds program memory write timing remark the dashed line indicates high-impedance. program memory read timing v pp v dd gnd v dd + 1 gnd v dd clk v pp v dd d0-d7 md0 md1 md2 md3 t res t vps t vds t xh t xl data input data output data input data input ti t ds t dh t dv t df t ds t dh t ah t as t opw t m0s t m1r t pw t pcr t m1s t m1h t m3s t m3h v pp v dd gnd v dd + 1 gnd v dd clk v pp v dd d0-d7 md0 md1 md2 md3 t res t vps t vds t xh t xl t dad t had data output data output t i t dv t m3hr t dfr t pcr t m3sr hi-z hi-z l
31 pd17p709a data sheet u15723ej1v0ds 4. package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 ? 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h
32 pd17p709a data sheet u15723ej1v0ds 5. recommended soldering conditions the pd17p709a should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 5-1. surface mounting type soldering conditions pd17p709agc-3b9: 80-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher.), ir35-00-3 count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher.), vp15-00-3 count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
33 pd17p709a data sheet u15723ej1v0ds appendix development tools the following development tools are available for development of programs for the pd17p709a. hardware name outline ie-17k-et is an in-circuit emulator that can be used with any model in the 17k series. ie-17k-et is connected to a host machine, which is pc-9800 series or ibm pc/at tm , with rs-232c. by using these in-circuit emulators with a system evaluation board (se board) corresponding to each model, these emulators operate as emulators specific to a model. when man-machine interface software simplehost tm is used, a more sophisticated debugging environment can be created. se-17709 is an se board for the pd17709a subseries. this board can be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. ep-17k80gc is an emulation probe for the pd17p709agc. by using this probe with ev-9200gc- 80 note 2 , the se board and target system are connected. ev-9200gc-80 is a conversion socket for 80-pin plastic qfp (14 14). it is used to connect the ep- 17k80gc and target system. pg-1500 is a prom programmer supporting pd17p709a. it can program the pd17p709a when connected with the pg-1500 adapter pa-17kdz and programmer adapter pa-17p709gc. pa-17p709gc is an adapter to program the pd17p709a. it is used with pg-1500. notes 1. external power supply type 2. one ev-9200gc-80 is supplied with the ep-17k80gc. five ev-9200gc-80 are also available as a set. remark third-party prom programmers af-9703, af-9704, af-9705, and af-9706 are available from ando electric co., ltd. use these programmers with programmer adapter pa-17p709gc. for details, consult ando electric co., ltd. (tel: +8-44-549-7300). software name outline host machine os media parts number 17k series pc-9800 series japanese windows tm 3.5 2hd saa13ra17k assembler (ra17k) ibm pc/at japanese windows 3.5 2hc sab13ra17k compatibles english windows sbb13ra17k device file pc-9800 series japanese windows 3.5 2hd saa13as17704 (as17704) ibm pc/at japanese windows 3.5 2hc sab13as17704 compatibles english windows sbb13as17704 support pc-9800 series japanese windows 3.5 2hd saa13id17k software ( simplehost ) ibm pc/at japanese windows 3.5 2hc sab13id17k compatibles english windows sbb13id17k in-circuit emulator (ie-17k-et note 1 ) se board (se-17709) emulation probe (ep-17k80gc) conversion socket (ev-9200gc-80 note 2 ) prom programmer (pg-1500) programmer adapter (pa-17p709gc) ra17k is an assembler that can be commonly used with 17k series. to develop programs for the pd17p709a, this ra17k and a device file (as17704) are used in combination. as17704 is a device file for the pd17p709a. it is used with the assembler common to the 17k series (ra17k). simplehost is man-machine interface software that runs on windows when a program is developed by using an in-circuit emulator and personal computer.
34 pd17p709a data sheet u15723ej1v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
35 pd17p709a data sheet u15723ej1v0ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
2 pd17p709a simplehost is a trademark of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of international business machines corporation. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. m8e 00. 4 the information in this document is current as of september, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a pa rticular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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